1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device such as a DRAM and a method of manufacturing the same.
2. Description of the Related Art
A conventional DRAM memory cell having one transistor and one capacitor will be described with reference to FIG. 10.
In manufacturing a conventional DRAM memory cell, a field insulator film 305 is formed first on a silicon substrate 301 by a localized oxidation of silicon (LOCOS) method, and then ion implantation of impurities for threshold voltage regulation is performed into the silicon substrate 301 by using the field insulator film 305 as a mask. Next, a polysilicon film is formed by a chemical vapor deposition (CVD) method and ion implantation of impurities for resistance reduction is performed, and thereafter patterning is applied thereto by etching so as to form a gate electrode 302.
Next, ion implantation of impurities is performed in the silicon substrate 301 by using the gate electrode 302 and the field insulator film 305 as a mask thereby forming a source region 303 and a drain region 304.
Next, a polysilicon film 307, a capacitor insulator film 308 and a polysilicon film 309 are successively formed by CVD method, thermal oxidation and CVD, respectively, thereby to form a stack capacitor. Thereafter, an interlayer insulator film 310 is formed by undoped silicade glass (NSG) or boron phosphorus silicade glass (BPSG) and a contact hole is formed to reach the drain region 304. Thereafter a metallic interconnection 311 such as aluminum is formed thereby to form a DRAM memory cell. Besides, 303 represents a semiconductor region, and 306 represents a gate insulator film. Such a DRAM memory cell has been disclosed in JP-A-1-119054 for instance.
Conventionally, an occupied area per DRAM cell is determined by a distance between the field insulator film 305 and the gate and a gate length, and these lengths have limits for reduction. Thus, the occupied area per cell has its limit for reduction. As a result, it has been difficult to achieve integration of memory cells in high density. Further, it involves a problem that a leak current is produced from a transistor forming the DRAM cell.